View HI1166_793601.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 2000 HI1166 8-bit, 250 msps, flash a/d converter the HI1166 is an 8-bit, ultra high speed, ?sh analog-to- digital converter ic capable of digitizing analog signals at a maximum rate of 250 msps. the digital i/o levels of the converter are compatible with ecl 100k/10kh/10k. applications spectrum analyzers video digitizing radar systems communication systems direct rf down-conversion digital oscilloscopes features differential linearity error . . . . . . . . . . 0.5 lsb or less integral linearity error . . . . . . . . . . . . . 0.5 lsb or less built-in integral linearity compensation circuit ultra high speed operation with maximum conversion rate (min) . . . . . . . . . . . . . . . . . . . 250 msps low input capacitance 18pf (typ) wide analog input bandwidth (min for full scale input) . . . . . . . . . . . . . . . . . . . 250mhz single power supply . . . . . . . . . . . . . . . . . . . . . . . . -5.2v low power consumption . . . . . . . . . . . . . . . . . 1.4w (typ) low error rate capable of driving 50 ? loads evaluation board available direct replacement for sony cxa1166k pinout HI1166 (clcc) top view part number information part number temp. range ( o c) package pkg. no. HI1166ail -20 to 100 68 ld clcc j68.a HI1166-ev 25 evaluation board dv ee d1 d1 d0 d0 or or linv nc av ee av ee v rts v rt nc av ee nc nc av ee nc agnd v in1 v in1 agnd v rm agnd v in2 v in2 agnd nc nc nc nc nc nc d2 d2 d3 d3 dgnd2 dgnd2 dgnd1 d4 d4 d5 d5 nc nc nc nc agnd nc 9 876543216867666564636261 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 nc dv ee d6 d6 d7 d7 minv clk clk nc av ee av ee v rbs v rb nc av ee agnd august 2000 file number 3579.5 [ /title (hi116 6) /sub- ject (8- bit, 250 msps, flash a/d con- verter) /autho r () /key- words (inter- sil corpo- ration, video, oscil- loscop e, com- muni- cation, radar, rf down con- ver- sion) /cre- ator () /doci nfo pdf- mark for a possible substitute pr oduct call central applications 1-888-intersil or email: centapp@inter sil.com obsolete pr oduct
2 functional block diagram 255 254 r/2 r r r5 193 r 191 r 192 r 129 r 128 r 127 r 126 r r3 v rm v in2 v rb clock driver 65 r 63 r 64 r 2 r 1 v in1 r r/2 v rt r1 comparator minv encode logic linv output d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) clk clk 33 r2 64 65 0 v rts 55 54 52 49 50 r4 39 40 v rbs 34 35 1 5 4 6 12 14 19 21 29 31 7 13 15 20 22 30 32 3 2 or or d7 d6 d5 d4 d3 d2 d1 d0 HI1166
3 absolute maximum ratings t a = 25 o c thermal information supply voltage (av ee , dv ee ) . . . . . . . . . . . . . . . . . . . . -7v to +0.5v analog input voltage (v in ). . . . . . . . . . . . . . . . . . . . . -2.7v to +0.5v reference input voltage v rt , v rb , v rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7v to +0.5v |v rt -v rb | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v digital input voltage minv, linv, clk, clk . . . . . . . . . . . . . . . . . . . . . . . . -4v to +0.5v |clk- clk| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v v rm pin input current (i vrm ) . . . . . . . . . . . . . . . . . . -3ma to +3ma digital output current (id0 to id7, ior, id0 to id7, ior) . . . . . . . . . . . . . -30ma to 0ma temperature range, t a (note 5) . . . . . . . . . . . . . . . -20 o c to 100 o c t c . . . . . . . . . . . . . . . . . . . . . -20 o c to 125 o c thermal resistance (typical, note 2) ja o c/w jc o c/w clcc package. . . . . . . . . . . . . . . . . . . 38 10 maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1w maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .175 o c maximum storage temperature range (t stg ). . . . -65 o c to 150 o c maximum lead temperature (soldering, 10s). . . . . . . . . . . . .300 o c operating conditions (note 1) supply voltage min typ max av ee , dv ee . . . . . . . . . . . . . . . . . . . . . . . -5.5v -5.2 -4.95v av ee - dv ee . . . . . . . . . . . . . . . . . . . . . . -0.05v 0 0.05v agnd - dgnd . . . . . . . . . . . . . . . . . . . . . -0.05v 0 0.05v reference input voltage min typ max v rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1v -2 0.1v v rb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2v -2 -1.8v analog input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . .v rb to v rt caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. notes: 1. electrical speci?ations guaranteed within stated operating conditions. 2. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations t a = 25 o c, av ee = dv ee = -5.2v, v rt , v rts = 0v, v rb , v rbs = -2v (note 1) parameter test conditions min typ max unit system performance resolution - 8 - bits integral linearity error, inl f c = 250 msps - 0.3 0.5 lsb differential linearity error, dnl f c = 250 msps - 0.3 0.5 lsb dynamic characteristics signal to noise ratio, sinad input = 1khz, full scale f c = 250mhz 44 46 - db input = 60khz, full scale f c = 250mhz -37-db error rate input = 50mhz, full scale error > 16 lsb, f c = 250mhz --10 -9 tps (note 3) input = 62.499mhz, full scale error > 16 lsb, f c = 250mhz -10 -8 10 -6 tps (note 3) differential gain error, dg ntsc 40 ire mod. ramp, f c = 250 msps - 1.0 - % differential phase error, dp - 0.5 - degree overrange recovery time - 1.0 - ns maximum conversion rate, f c 250 - - msps aperture jitter, t aj -9-ps sampling delay, t ds 0.4 1.4 2.4 ns analog input analog input capacitance, c in v in - 1v + 0.07v rms -18-pf analog input resistance, r in 50 120 - k ? input bias current, i in v in = -1v 20 - 450 a full scale input bandwidth v in = 2v p-p 200 250 - mhz reference inputs reference resistance, r ref 83 125 182 ? rms signal rms noise distortion + ----------------------------------------------------------------- - = HI1166
4 timing diagram residual resistance r1 note 2 0.1 0.6 2.0 ? r2 300 500 700 ? r3 0.5 2.0 5.0 ? r4 300 500 700 ? r5 0.1 0.6 2.0 ? digital inputs logic h level, v ih -1.13 - - v logic l level, v il - - -1.5 v logic h current, i ih input connected to gnd 0 - 70 a logic l current, i il input connected to -2v -50 - 50 a input capacitance -4-pf digital outputs logic h level, v oh r l = 50 ? -1.0 - - v logic l level, v ol r l = 50 ? - - -1.6 v timing characteristics h pulse width of clock, t pw1 1.8 - - ns l pulse width of clock, t pw0 1.8 - - ns output rise time, t r r l = 50 ? - 0.6 1.5 ns output fall time, t f r l = 50 ? - 0.6 1.5 ns output delay, t od r l = 50 ? 1.8 2.5 3.2 ns power supply characteristics supply current, i ee -360 -270 - ma power consumption, p d note 4 - 1.4 1.9 w notes: 1. electrical speci?ations guaranteed within stated operating conditions. 2. see functional block diagram. 3. tps: times per sample. 4. 5. t a is specified in still air and without heat sink. to extend temperature range, appropriate heat management techniques must be employed (see figure 2). electrical speci?ations t a = 25 o c, av ee = dv ee = -5.2v, v rt , v rts = 0v, v rb , v rbs = -2v (note 1) (continued) parameter test conditions min typ max unit pd i eea av ee i eed dv ee v rt v rb () 2 r ref ------------------------------------- + ? + ? = n n + 1 n + 2 n + 1 n n - 1 20% 80% t r t od t f t pw1 t pw0 80% 20% analog in clk clk digital out t sd figure 1. HI1166
5 typical performance curves figure 2. thermal resistance of the converter mounted on a board figure 3. v in pin capacitance vs voltage characteristics figure 4. v in pin input resistance vs voltage characteristics figure 5. v in pin input current vs voltage characteristics figure 6. v in pin input current vs temperature characteristics figure 7. resistor string current vs temperature characteristics socket amp: 173061-5 (without heat sink) socket amp: 173257-3 (with heat sink) socket: yamaichi electronics co., ltd ic61-0684-048 1.0 air flow (m/s) 2.0 3.0 0 30 40 50 thermal resistance ja ( o c/w) input capacitance (pf) input voltage (v) 25 20 15 10 -2.0 -1.5 -1.0 -0.5 0 analog input resistance (k ? ) input voltage (v) 150 125 100 10 -2.0 -1.5 -1.0 -0.5 0 i in ( a) input voltage (v) 200 100 0 -2.0 -1.5 -1.0 -0.5 0 input current ( a) 200 150 100 0 50 case temperature ( o c) -50 0 50 100 150 resistor string current (ma) case temperature ( o c) -12 -16 -20 -24 -50 0 50 100 150 -14 -18 -22 HI1166
6 figure 8. clk open voltage vs temperature characteristics figure 9. v oh vs temperature characteristics figure 10. v ol vs temperature characteristics figure 11. sinad vs input frequency response characteristics figure 12. harmonic distortion vs input frequency response characteristics figure 13. maximum conversion rate vs temperature characteristics typical performance curves (continued) clk open voltage (v) case temperature ( o c) -1.25 -1.35 -1.40 -1.45 -50 0 50 100 150 -1.30 v oh (v) case temperature ( o c) -0.7 -0.9 -1.0 -1.1 -50 0 50 100 150 -0.8 v ol (v) case temperature ( o c) -1.7 -1.9 -2.0 -2.1 -50 0 50 100 150 -1.8 sinad (db) input frequency (mhz) 50 40 35 25 1 10 100 45 30 high frequency distortion (db) input frequency (mhz) -30 -50 -60 -80 0.1 1 10 -40 -70 100 1000 clock frequency = 250mhz third harmonic second harmonic clk (mhz) ambient temperature ( o c) 250 200 -25 25 75 150 125 error rate = 10-8 tps input frequency = clock frequency/4 - 1khz error rate > 16 lsb 300 HI1166
7 figure 14. error rate vs conversion rate figure 15. error rate vs clock duty cycle figure 16. supply current vs temperature characteristics typical performance curves (continued) error rate (tps) clock frequency (mhz) 10 -8 10 -9 200 250 10 -10 300 input frequency = clock frequency/4 - 1khz error rate > 16 lsb 10 -7 error rate (tps) clk duty cycle (%) 10 -7 10 -8 25 35 50 10 -9 60 input = 125mhz, full scale clk = 250mhz, error rate > 16 lsb 30 40 45 55 65 70 case temperature ( o c) -200 -250 -300 -350 -50 0 50 100 150 supply current (ma) pin descriptions pin number symbol i/o standard voltage level equivalent circuit description 4, 5 d0, d0 o ecl lsb and complementary lsb output. 6, 7 d1, d1 d1 to d6: data output. d1 to d6: complementary data out- put. 12, 13 d2, d2 14, 15 d3, d3 19, 20 d4, d4 21, 22 d5, d5 29, 30 d6, d6 31, 32 d7, d7 msb complementary msb data output. 2, 3 or, or overrange and complementary overrange output. dv ee dgnd2 di di 16 8 28 HI1166
8 1 linv i ecl polarity selection for lsbs (refer to the a/d output code table.) pulled low when left open. 33 minv i ecl polarity selection for msb (refer to the a/d output code table). pulled low when left open. 35 clk i ecl clk input. 34 clk i ecl complementary clk input. pulled down to -1.3v when left open. 64 v rt i 0v analog reference voltage (top) (0v typ). 65 v rts o 0v reference voltage sense (top). 52 v rm iv rb/2 reference voltage mid point. can be used for linearity compensation. 39 v rbs o -2v reference voltage sense (bottom). 40 v rb i -2v analog reference voltage (bottom). pin descriptions (continued) pin number symbol i/o standard voltage level equivalent circuit description r r r r -1.3v dv ee dgnd1 linv or minv 18 1 33 8 28 dv ee clk clk dgnd1 r r r r rr 8 28 35 34 18 r/2 r v rt r1 r2 r r3 v rm r/2 v rbs r4 64 65 v rts 52 39 r5 40 v rb to comparators r HI1166
9 49, 50 v in2 iv rts to v rbs analog input. all of the pins must be wired externally. 54, 55 v in1 43, 48, 51, 53, 56, 61 agnd 0v analog ground. 37, 38, 42, 58, 62, 66, 67 av ee -5.2v analog supply. internally connected to dv ee (resistance: 4 ? to 6 ? ). 18 dgnd1 0v digital ground. 16, 17 dgnd2 0v digital ground for output drive. 8, 28 dv ee -5.2v digital supply. internally connected to av ee (resistance: 4 ? to 6 ? ). table 1. a/d output code v in (note 6) step minv 1, linv 1 0, 1 1, 0 0, 0 or d7 d0 or d7 d0 or d7 d0 or d0 d7 0v 0 000 ?????00 0 100 ?????00 0 011 ?????11 0 111 ?????11 0 1 000 ?????00 1 100 ?????00 1 011 ?????11 1 111 ?????11 1 1 000 ?????01 1 100 ?????01 1 011 ?????10 1 111 ?????10 -1v 127 1 011 ?????11 1 111 ?????11 1 000 ?????00 1 100 ?????00 128 1 100 ?????00 1 000 ?????00 1 111 ?????11 1 011 ?????11 254 1 111 ?????10 1 011 ?????10 1 100 ?????01 1 000 ?????01 255 1 111 ?????11 1 011 ?????11 1 100 ?????00 1 000 ?????00 -2v 1 111 ?????11 1 011 ?????11 1 100 ?????00 1 000 ?????00 note: 6. v rt = v rts = 0v, v rm = -1v or open, v rb = v rbs = -2v. pin descriptions (continued) pin number symbol i/o standard voltage level equivalent circuit description agnd 43, 48, 51, 53, 56, 61 to comp. 128 to 255 54 0 to 127 55 v in1 v in2 50 49 av ee agnd 61 43 51 56 48 53 internal analog circuit internal digital circuit 18 16 17 dgnd1 dgnd2 d1 d1 8 28 62 42 37 58 38 66 67 dv ee 4 ? to 6 ? HI1166
10 test circuits and waveforms figure 17. maximum conversion rate test circuit figure 18. integral and differential linearity error test circuit signal source ntsc sg (cw) v in 8 8 scope vector dg/dp func. amp HI1166 dut ecl d/a 10-bit -4.5v clk 1 2 oscillo- hi20201 generator 2 ? divider 50 duty clk latch 110 110 100 100 scope 1 2 amp maximum conversion rate 0v -2v fms switch position 1. maximum conversion rate 2. dg/dp - v in HI1166 dut 8 clk (250mhz) + ab comparator a8 a1 a0 b8 b1 b0 ? ? 8 s1 s2 -v +v s1 : a < b : on s2 : a > b : on buffer dvm controller 8 to 111 ???10 000 ???00 to to HI1166
11 figure 19. power supply and analog input bias current test circuit where (unit: lsb) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. figure 20a. figure 20b. aperture jitter test method figure 20. sampling delay and aperture jitter test circuit test circuits and waveforms (continued) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 i eed -5.2v a i eea -5.2v a i in -1v a -2v HI1166 v in HI1166 8 clk logic analyzer 1024 samples ecl buffer amp osc1 : variable osc2 60mhz 60mhz f r aperture jitter (lsb) 129 128 127 126 125 0v -1v -2v v in clk v in clk ? ? t t t aj ? ? t ------- ? 256 2 --------- - 2 f ?? ?? ? == aperture jitter is defined as follows: HI1166
12 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com HI1166

▲Up To Search▲

Price & Availability of HI1166

	To Download HI1166 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .